Sr Principal Application Engineer - Emulation
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. In this role, you will develop customer specific emulation and prototyping requirements, including advanced acceleration component development, methodology support, and operation and maintenance of Cadence’s emulation and prototyping tools and services. You will support technical evaluations and benchmark development for Cadence’s market leading tools such as Palladium acceleration and emulation platform and Protium prototyping platform. You will create and conduct technical presentations and product demonstrations for customers.
Responsibilities
Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support Provide in-depth technical assistance in collaboration with R&D to help support advanced verification flows to secure design wins Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions Understand the competitive landscape and continuously work on differentiating Cadence’s solutions Write technical product literature such as application notes and technical articles Review new product proposals and device specifications Assume technical leadership roles in team as needed
Requirements
Minimum: MS.or PhD degree in Computer Science, Engineering, or related field Strong RTL and Testbench debug skills Experience in Synthesizable coding style Experience in writing scripts (Perl, Python or TCL) Strong software, HDL design and verification skills Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze verification environments and design complexity Strong verbal and written communication skills Strong teamwork skills Ability to interact effectively with both external customers and R&D teams 5+ years industry experience Preferred: Experience in HW acceleration, in-circuit Emulation or FPGA prototyping Experience with multiple clock domains and asynchronous interfaces Knowledge of the FPGA development process & tool flow from RTL to bitstream for Xilinx and/or Altera products Hands on experience with lab bring up, debug, chipscope and instrument usage Experience with C/C++/SystemC Knowledge of fundamental SoC Architecture knowledge Understanding of embedded software development and HW/SW co-design and co-verification Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR, CHI Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing We’re doing work that matters. Help us solve what others can’t.